Welcome to Course - Introduction
Verification Basics and Concepts
-
Verification - What , Why and How ? (7:23)
-
Verification - Planning, Approaches, Metrics (9:17)
-
Verification Methodologies - Simulation , Formal and Assertions (13:57)
-
Directed Vs Constrained Random Verification and Coverage (12:59)
-
Other Trends - HW+SW Verification and Emulation (8:14)
-
Quiz 2: Test your Verification Concepts
-
Exercise 1: Case Study with a Design to be verified (9:08)
Introduction to System Verilog Language
-
History and Overview of System Verilog (6:20)
-
Language Constructs: DataTypes And Operators (10:41)
-
Language Constructs: Loops and Flow control (6:59)
-
System Verilog Tasks and Functions (5:06)
-
Quiz 3 : Test your SystemVerilog Basics
-
SV Arrays and Queues (13:53)
-
Exercise 2: Coding of a design to be verified (18:39)
Basic System Verilog Test bench Constructs
System Verilog - OOP Concepts and Randomization
Threads and Inter Process Communication
Introduction to Verification Methodologies
Course Wrap up and Summary
