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Learn to Build UVM Testbenches from Scratch
Introduction and Welcome
Introduction and Welcome to Course (3:33)
Course Resources and Instructions (2:53)
Need for Standard Verification Methodologies (13:58)
Layered Testbench Architecture (14:56)
Download Course Resources And Assignment Instructions (18:39)
Fundamentals of OVM/UVM - Transaction Level Modelling Concepts
Introduction to OVM/UVM Concepts (7:12)
Transaction Level Modelling Basics (15:01)
TLM Interfaces - Ports, Exports and FIFOs (15:01)
TLM Interfaces - Analysis Ports and FIFOs (3:41)
Assignment 1 - Producer Consumer Example with TLM1 - Coding and Simulating (7:32)
Quiz1: Test your basics on TLM
Building Testbench Components
Testbench Component And Hierarchy (14:59)
Building Driver and Sequencer Components (13:53)
Sequencer to Driver Connection (11:34)
Building a Monitor Component (8:00)
Building an Agent Component (9:58)
Environment and Test Class Components (9:53)
Building and Connecting Testbench Components (15:01)
Understanding Simulation Phases (13:23)
Quiz 2: Test your basics on testbench components
Sequence Based Stimulus Generation
Basics of Sequence based Stimulus Generation (14:27)
Sequence Items and Methods (15:01)
Sequences and its Methods (15:01)
Sequencer and Driver APIs (14:45)
Sequence Generation Styles (8:13)
Basics of Virtual Sequences (7:28)
Dynamic Construction and Configuration
Messages and Reporting in UVM
Basics of OVM/UVM Factory (15:01)
End of Test Mechanisms
Testbench Configuration in UVM (12:56)
Project Assignment - Building a real Testbench
Assignment Overview (5:14)
Introduction to APB Protocol (8:48)
APB Testbench Architecture (5:05)
Creating APB Transaction and Interface (3:33)
Creating APB Driver and Sequencer (2:33)
Creating APB Monitor (2:09)
Creating APB Agent and Environment Components (3:04)
Creating APB Sequences (2:16)
Building Test, Top level Module and Running Simulation (4:40)
Summary
Summary of Course (6:48)
Online Exam
Teach online with
Environment and Test Class Components
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