UVM (Universal Verification Methodology) is a SystemVerilog language based Verification methodology which is getting more and more popularity and adoption in the VLSI Verification industry. The methodology is currently in the IEEE working group 1800.2 and is expected to be an IEEE standard shortly.

UVM consists of a defined methodology for architecting modular testbenches for design verification. UVM has a library of classes that helps in designing and implementing modular testbench components and stimulus. This enables re-using testbench components and stimulus within and across projects, development of Verification IP, easier migration from simulation to emulation etc.

The adoption of UVM as standard methodology is growing at a fast pace across industry and it is important for every verification engineer and new engineers aspiring a career in Verification to learn this skill.

Given the complex nature of UVM, lack of good and easy documentation and need for understanding more software skills in addition to hardware design skills, even an experienced engineer find it hard to master UVM and its usage.

If you are preparing for a Verification job interview or if you are trying to master this methodology for your next project, here are some of the questions that you can use to test your skills and measure yourself:

  1. What are some of the benefits of UVM methodology?
  2. What are some of the drawbacks of UVM methodology?
  3. Explain the concept of Transaction Level Modelling?
  4. What is the difference between an uvm_object and uvm_component class?
  5. What are TLM ports and TLM Fifos?
  6. What is an analysis port and analysis fifo and where are they used?
  7. Explain the protocol handshake between a sequencer and driver ?
  8. What is the difference between a sequence and sequence item?
  9. Is it possible to collect responses from DUT back to a sequence and if so how?
  10. What is the difference between SEQ_ARB_RANDOM and SEQ_ARB_STRICT_RANDOM arbitration mechanism on sequencer?
  11. What is the difference between grab() and lock() on sequencer?
  12. What is the difference between a pipelined and non-pipelined driver?
  13. What is the difference between early randomization and late randomization of sequences?
  14. Write a sample sequence code that generates a stream of ethernet packets?
  15. How can you specify weightage for a sequence when started on a sequencer?
  16. What is the difference between a monitor and a scoreboard in UVM methodology?
  17. What is meant by factory and what is its importance?
  18. What is the difference between creating an object using new() and create()?
  19. What are the difference phases in UVM and what is the order of their execution?
  20. What are objections and how are they useful?
  21. How can you implement a simulation timeout mechanism using UVM methodology?
  22. What is meant by factory override and what are different types of overriding possible with UVM factory?
  23. What is a virtual sequence and where do we use a virtual sequence? What are its benefits?
  24. What is uvm_config_db and what is it used for?
  25. Why should any uvm component be registered with factory?

Well done if you got correct answers for these questions !

That shows you have good understanding on UVM to have that exciting and challenging job in Design Verification.

If you need some improvement or you want to know answers, then our book - "Cracking Digital VLSI Verification Interview: Interview Success" has a dedicated chapter that explains answers to all these in detail.

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