This question arises in every one's mind while preparing for a Verification Interview. A lot of times in addition to understanding the technical concepts, you also needs to focus your preparation aligning with expectations from the interviewer and practice some of the commonly asked questions. This helps you to gain confidence and answer any related questions during that crucial interview time and increase your chances for success.

Based on my more than a decade of interview experience, I wanted to share some details on how I go about interviewing:

I always start testing the candidate's thinking ability on a given design to be verified. I usually give him a simple design and specification (eg: a full adder or a simple ALU or a simple cache or a Multi master bus or a SRAM controller or anything of that sort). This helps me to ask several follow on questions and evaluate how well the candidate knows about verification and how well he thinks through, given a problem. The more the candidate answers, I go in more depth and ask more questions on his approach, the verification methodology, stimulus generation styles, assertions, checkers etc etc. This process tells me how far a candidate can think through.

Clearly current ASIC designs are trending more to System on Chip (SOC) designs and with increasing complexity in developing test benches and simulation models, software programming concepts and skills are a must for any Verification engineer.

So I follow with asking at least a few questions to evaluate the programming skills of candidate (say a given problem/algorithm that needs some code to be written in languages like C/C++/SystemVerilog or any language candidate is comfortable with) as well as basic programming concepts. It doesn't matter which language but the candidate should know the fundamentals of programming concepts very clear.

Based on how experienced the candidate is, I then follow with questions on digital logic design (related to logic gates/state machines/sequential circuits etc), verification methodologies like OVM/UVM, object oriented programming concepts etc.

And lastly I also ask questions related to his past work experience as per resume which helps to judge how well he has performed in past. This is important as the past performance is a clear indication of how he will perform in the future. I have seen a lot of candidates with fake/weak experience falling out in a few levels of Why and How questions related to the project experience.

If you are interested to hear from more Verification leaders in industry with several decades of experience and learn more tips, then my recent book on "Cracking Digital VLSI Verification Interviews: Interview Success" has a dedicated section that interviews some of the best leaders I have worked with.

Read them and then focus your preparation by practicing some of the commonly asked questions. You can find a lot of them in the same book. Not that only these questions get asked in an interview but this will help your preparation. Robin (my co-author) and myself also tried to put some extra focus on the latest and greatest Verification methodologies like UVM and System Verilog following the latest trend. Just these sections alone has more than 200+ questions. Check this book teaser here.

As authors of the book, myself and Robin honestly wish that you succeed in your interviews and have a great career !



The book is available on Amazon in following URL


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